STEPLA-1: An 8-bit Hardwired CPU Built by 2nd Year EE Students

Two second-year electrical engineering students built and simulated a fully functional 8-bit CPU called STEPLA-1, version 2.4.2, in Logisim-Evolution. The CPU is built entirely from individual logic gates down to the gate level—no black box components. Every signal path is visible, traceable, and documented.

Architecture

STEPLA-1 implements a Harvard architecture with separate 256-byte instruction and data RAM. It has 16 instructions, each with a 4-bit opcode, and 4 general-purpose registers (RA-RD). The control unit is fully hardwired using a PLA-inspired gate matrix with hierarchical decode: opcode decoder + step decoder + AND matrix. No EEPROM, no microcode—pure combinational logic. Every control signal is traceable to individual gates.

Performance

Instructions take 3 to 5 clock cycles. Conditional branching uses an early-exit mechanism that reduces latency by 25%. The synchronous load-to-one reset achieves a 33% efficiency gain over version 2.3. Calculated IPC ranges from 0.200 to 0.333, with a weighted average of 0.263. The target clock is 4 MHz on a physical breadboard, yielding an effective throughput of approximately 1 MIPS.

Instruction Set

The instruction set includes:

  • NOP (0x0, 3 cycles)
  • HLT (0x1, 3 cycles)
  • ADD (0x2, 5 cycles)
  • SUB (0x3, 5 cycles)
  • MOV (0x4, 3 cycles)
  • MOVI (0x5, 4 cycles)
  • STRD (0x6, 4 cycles)
  • OUT (0x7, 3 cycles)
  • JMP (0x8, 4 cycles)
  • JZ (0x9, 3/5 cycles, early exit)
  • JC (0xA, 3/5 cycles, early exit)
  • LDIM (0xB, 5 cycles)
  • LDD (0xC, 4 cycles)
  • GETPC (0xD, 3 cycles)
  • JP (0xE, 3 cycles)
  • STIM (0xF, 5 cycles)

Comparison with SAP-1

Compared to Ben Eater's SAP-1, STEPLA-1 has 16 instructions vs. 5, 4 general-purpose registers vs. 2 fixed-purpose, 256 bytes of RAM vs. 16, and a hardwired control unit vs. EEPROM microcode. It also supports conditional jumps (JZ, JC) with early exit, a bootstrap control unit (BCU) for cold-boot ROM-to-RAM transfer, and a target clock of 4 MHz vs. ~1 MHz, achieving ~1 MIPS vs. ~0.17 MIPS.

Getting Started

To run the simulation, clone the repository and open simulation/STEPLA-1.circ in Logisim-Evolution v3.8.0 or later. Load a program (e.g., programs/fibonacci.asm) into the ROM, toggle the switch to 1, press reset, and run the clock. The BCU automatically copies ROM contents to instruction RAM before releasing control to the CPU.

Documentation

The full 43-page specification covers control unit theory, complete ISA with encoding rules, every instruction's T-state microoperation sequence, clock phase synchronization, BCU boot protocol, signal conditioning for physical build, timing analysis with real component datasheets, and known limitations with a v3.0 roadmap.

Physical Build

STEPLA-1 is designed for physical construction using 74HCT series logic. Key components include 74HCT08, 74HCT32, 74HCT14, 74HCT86 for logic; 74HCT377, 74HCT175, 74HCT74 for registers; 74HCT154, 74HCT138, 74HCT139 for decode; 74HCT163 for counter; 74HCT283 (×2 cascaded) for ALU; AS6C62256 SRAM and AT28C64B EEPROM for memory; and 74HCT244, 74HCT245 for bus. Target clock speed is 4 MHz, verified via timing analysis with a critical path of 101ns and half-cycle budget of 125ns at 4 MHz.

Roadmap

Planned features for v2.5.0 include overflow flag (VF) and negative flag (NF), signed arithmetic support, JV and JN conditional jump instructions, and Proteus ISIS simulation. v3.0.0 plans a 16-bit instruction word, 16-register general-purpose file, hardware stack (PUSH/POP/CALL/RET), dual asynchronous control units, and a pre-fetch buffer approaching 1.0 CPI.

Conclusion

STEPLA-1 is a transparent, fully documented, and physically realizable 8-bit CPU design. It offers a middle ground between EEPROM microcode and HDL simulation, where every gate maps to a real 74-series IC. The repository includes simulation files, assembly programs, and a full specification. Contributions are welcome, especially for physical build documentation, additional programs, an assembler, or Proteus port.

Check out the GitHub repository and the full 43-page specification to start building or simulating your own STEPLA-1.