DRAM Read Disturbance: The Gap Between Theory and Reality

DRAM read disturbance—RowHammer and RowPress—remains a critical robustness issue. Accessing DRAM can cause unintended bitflips in unaccessed locations. These bitflips threaten system safety, security, and reliability. Prior work either experimentally characterized bitflips or modeled underlying physics. But the two camps rarely agree.

A new arXiv paper (2607.28233) from Haocong Luo and colleagues bridges this gap. The authors identify inconsistencies between existing device-level models and experimental data. They then present comprehensive TCAD simulations that match real-chip behavior. The result: updated error mechanisms and key modeling parameters for future work.

Three Fundamental Metrics That Don't Add Up

The paper focuses on three metrics that should map to first-order physical mechanisms:

  1. Bitflip directions – whether bits flip from 1 to 0 or 0 to 1.
  2. Bitflip counts – how many bits flip per aggressor row activation.
  3. ACmin – the minimum number of aggressor row activations to trigger the first bitflip.

Existing models fail to explain all observed patterns. For example, RowHammer typically flips bits in one direction, while RowPress shows different behavior. The paper demonstrates these gaps with concrete examples.

TCAD Simulations: Matching Real Chips

To address the gaps, the authors ran TCAD (Technology Computer-Aided Design) simulations. They modeled DRAM cells and wordline drivers under repeated access. The simulations reproduced key phenomena seen in experimental characterizations.

Key findings:

  • Bitflip direction depends on the initial charge state and the polarity of the disturbance. The simulations show that RowHammer can cause both 0-to-1 and 1-to-0 flips, depending on the data pattern.
  • Bitflip count scales with the number of activations, but saturates after a certain point—matching experimental saturation curves.
  • ACmin varies with the hammering pattern and the physical parameters of the cell, such as the oxide thickness and doping profile.

The paper identifies specific simulation parameters that significantly affect whether results match real chips. These include the interconnect capacitance, the access transistor's threshold voltage, and the storage capacitor's dielectric leakage. Adjusting these in the simulation can make the difference between matching or missing experimental data.

Updated Error Mechanisms

Based on the simulations, the authors propose updated device-level mechanisms:

  • RowHammer is primarily driven by electron injection into the floating body of the access transistor, causing a threshold voltage shift. This matches the observed directionality and ACmin behavior.
  • RowPress involves a slower charge leakage path through the gate oxide, which explains why it requires fewer activations but a longer hold time.

These mechanisms are more nuanced than previous models, which often treated both as a single phenomenon.

Implications for Mitigation and Characterization

The paper offers practical implications:

  • Characterization methodologies should measure bitflip direction and count separately, not just total bitflip rate. This provides richer data for model validation.
  • Mitigation techniques should account for the different mechanisms. For example, a refresh rate that works for RowHammer may not fully address RowPress.

What This Means for Developers

For developers working on memory controllers or system software, this research is foundational. It provides a more accurate model of when bitflips occur, which can inform error-correcting code (ECC) strategies and refresh policies.

One concrete takeaway: if you're designing a mitigation, you should consider the ACmin of your target DRAM. Knowing the minimum number of activations before a bitflip allows you to schedule refreshes or throttling more aggressively.

The Future: From Simulation to Practice

The paper doesn't provide a ready-to-use mitigation. But it gives the community a validated simulation framework. Future work can use these TCAD models to test new designs before fabrication.

If you're working on DRAM reliability, read the full paper on arXiv. The simulation parameters and methodology are detailed enough to reproduce.

Next Steps

  • Read the paper: https://arxiv.org/abs/2607.28233
  • Compare your own experimental data with the proposed mechanisms.
  • Consider incorporating ACmin and bitflip direction into your next error model.

The gap between physics and observed behavior is closing. Now it's up to the community to build on it.