Nvidia Locks SK Hynix for HBM4 Co-Development Ahead of Vera Rubin in 2026

Nvidia and SK Hynix have signed a multi-year agreement to co-design and manufacture next-generation high-bandwidth memory (HBM) for AI accelerators. The deal, announced during Jensen Huang's tour of South Korea, gives SK Hynix a formal co-development role for HBM4, the memory technology that will power Nvidia's Vera Rubin platform now entering full production.

Industry analysts estimate SK Hynix holds 60-70% of HBM4 volume allocated to Vera Rubin, with Samsung at 25-30% and Micron supplying the remainder. The multi-year commitment makes SK Hynix's position durable and allows the company to expand capacity aggressively.

Why Memory Became the Bottleneck

Arm CEO Rene Haas recently called memory "probably the toughest" bottleneck the industry must resolve. This isn't hyperbole. Each Vera Rubin NVL72 configuration connects 36 CPUs and 72 GPUs, requiring terabytes of HBM4. Advanced packaging—specifically TSMC's CoWoS process that integrates GPU dies with HBM—is a key constraint. Memory supply, not silicon fabrication, now paces how fast Nvidia can ship its highest-end systems.

Analysts at TrendForce describe the current situation as a "memory supercycle," with HBM capacity projected tight through at least 2028, possibly 2030. For Nvidia, locking SK Hynix into a co-development deal ensures supply exists at all.

What the Deal Covers

The partnership extends beyond a standard supply agreement. Nvidia and SK Hynix will co-develop next-generation memory for "AI factories"—large-scale data center clusters for training and inference. The scope covers infrastructure, physical AI, and memory specifically designed for Vera Rubin.

Vera Rubin delivers 3.5× the training performance and 5× the inference performance of its Blackwell predecessor. Shipments begin in Q3 2026, with over 350 supply chain partners across 30 countries involved in production.

Huang stated: "Together, we will co-develop the next generation of memory for AI factories and support the accelerating global expansion of AI infrastructure."

The HBM4 Race

Huang confirmed at Computex that all three major memory manufacturers—Samsung, SK Hynix, and Micron—have been cleared to supply HBM4 for Vera Rubin. But the co-development pact with SK Hynix signals a deeper relationship than standard vendor qualification.

All three firms race to deliver 16-layer HBM stacks that Nvidia reportedly requested for delivery as early as late 2026. Long-term supply commitments make capacity expansion easier and gradually increase market share.

Huang's Seoul Tour

The SK Hynix deal was part of broader announcements during Huang's visit. SK Telecom will build a gigawatt-scale AI cloud powered by Nvidia chips, with the first data center online early next year. Naver will use Nvidia's AI models to expand data center capacity and build additional gigawatt-scale AI factories. Doosan Group will use Nvidia's physical AI for industrial robotics.

Huang also threw the ceremonial first pitch at a KBO game, dined with SK Group Chairman Chey Tae-won, and visited gaming studios Krafton and NC Corp to promote Nvidia's RTX Spark chip.

What Developers Should Watch

This deal signals that memory architecture will be a key differentiator in AI hardware for years. Developers building for AI infrastructure should monitor HBM4 specifications and availability, as memory bandwidth directly impacts training and inference performance. The Vera Rubin platform's 5× inference improvement over Blackwell depends heavily on HBM4's bandwidth.

For those working with AI models, expect tighter coupling between model architecture and memory hierarchy. Nvidia's co-development approach means future SDKs and libraries may optimize for SK Hynix's specific HBM4 designs.

Bottom Line

Nvidia is securing its memory supply chain years in advance, recognizing that memory, not compute, is the binding constraint. The SK Hynix deal ensures co-optimized HBM4 for Vera Rubin, giving Nvidia a strategic edge over competitors who may face memory shortages. Developers should prepare for a memory-centric era in AI hardware design.