GFX1250: AMD's MI455X AI Accelerator Emerges from LLVM Patches

LLVM commits for AMD's GFX1250 (codenamed MI455X) reveal a radical departure from previous CDNA architectures. The accelerator powers the Helios rack and targets machine learning exclusively. Here's what the tea leaves show.

Wave32 Only, 20 Waves Per SIMD

GFX1250 operates exclusively in Wave32 mode. Prior CDNA GPUs used Wave64; RDNA could switch. This forces kernel rewrites for anyone porting from CDNA. Each SIMD can run 20 waves, four more than RDNA4.

1024 VGPRs Per Wave, No Dynamic Allocation

Each wave can address up to 1024 Vector General Purpose Registers (VGPRs) from the register file. CDNA4 split 256 VGPRs + 256 Accumulation VGPRs (total 512). RDNA4 caps at 256. Dynamic VGPR allocation (present in RDNA4) is missing — the instruction is a no-op. This is surprising for ML workloads with high register pressure.

Unified 448KB WGP Cache Replaces Split LDS/L0

GFX1250 merges LDS and vector L0 into a single 448KB WGP cache (WGP$). This matches Nvidia and Intel's approach. Maximum addressable LDS per wavefront is 320kB (up from 128kB in CDNA4, 64kB in RDNA). The cache is partitionable by the compiler.

WMMA Tensor Instructions: Best of CDNA4 and RDNA4

GFX1250 uses WMMA (from RDNA4) instead of MFMA (CDNA). Matrix dimensions: M=N=16, K varies by type. For fp16: K=32 (like CDNA4, not RDNA4's K=16). For fp8: K=64. For i4: K=32 (same as RDNA4). Sparse WMMA keeps K constant (less work per instruction). Supported types include OCP MX formats from CDNA4. fp64 is restricted to GFX1251 (MI430X).

Cluster-Level Barriers and DSMEM

GFX1250 introduces cluster-level barriers and cluster loads, enabling cross-workgroup LDS access (AMD's Distributed Shared Memory). This mirrors Nvidia's Hopper clusters. Also new: monitor intrinsics that notify a wave when a cache line is evicted from L2 — a feature without Nvidia equivalent.

Hardware Tanh, Faster FP32 Division

Hardware tanh support speeds up neural network activation functions. BF16 division added. FP32 division latency drops from 9 cycles (RDNA4) to 8 cycles.

128-Byte Atomic Loads/Stores

New intrinsics for 128B atomic loads/stores (32x4B, 16x8B, 8x16B). These are sequences of regular loads/stores that the hardware coalesces onto the bus. Not available over PCIe, but likely over CXL/UALink. This mirrors Nvidia's Tensor Memory Accelerator (TMA).

Stripped Graphics: No Rasterizer, No Textures

GFX1250 removes nearly all graphics features: no export instructions, no image/texture instructions, no BVH (raytracing), no parameter interpolation, no MTBUF or MUBUF instructions. Even more stripped than CDNA, saving die space.

DMA and Prefetch Enhancements

SDMA units inherited from CDNA with new tensor DMA variants. Explicit prefetching for vector memory added. Details on tensor DMA are opaque due to LLVM documentation gaps.

What This Means for Developers

  • Wave32 migration: Expect performance regressions on Wave64-optimized kernels. Profile and retune.
  • Register pressure relief: 1024 VGPRs enable larger tiles in matrix multiplies. Consider increasing workgroup sizes.
  • Unified LDS/cache: No more LDS vs. cache tradeoffs. Use compiler hints to partition the 448KB pool.
  • Cluster programming: New synchronization primitives require learning cluster-level barriers. Start experimenting with cooperative groups.
  • No dynamic VGPR allocation: Manual register management still needed. Use amdgpu_num_vgpr to control usage.

Conclusion

GFX1250 is a clean-sheet AI accelerator that borrows the best from CDNA4 (large register files, MX formats) and RDNA4 (WMMA, simpler programming). The unified cache, cluster support, and 128B atomics bring AMD closer to Nvidia's architectural maturity. Developers should start evaluating their ML kernels on Wave32 and prepare for a new programming model centered on clusters and DSMEM.